In this paper, a novel device, substrate fed threshold logic, is proposed for the implementation of threshold logic. Tolerances of threshold levels and weighting factors are calculated and applied to the substrate fed threshold logic device.
The collector current of the vertical pnp transistor, corresponding to the threshold level, is analyzed simply and it is investigated how the collector current can be obtained within the specified tolerance levals.
The effective current gain of the npn transistor is investigated including the effect of the back injection current. Especially, the effective current gain of the folded collector npn transistor is examined in terms of the back injection current, and it is investigated how the effective current gain of 1 can be obtained.
$Jcpn^-p/Jcpn^+p$ of 150, a delay - power product of 4,3 PJ and a minimum delay time of 41 nsec have been obtained from the chip fabricated.
The effective current gain of the folded collector npn transistor varied slightly with, the number of the injection windows. From these result, it is shown that threshold logic circuits can be implemented with the substrate fed threshold logic.
