One part of the digital watch, decade, devide by 6 counter, is fabricated with $I^2L$ technology.
In this paper, the basic theories, such as NPN Tr. upward current gain, PNP Tr. transfer ratio, propagation delay time, stacking of $I^2L$ chips etc., are explained briefly.
Besides this, the general design guidelines of $I^2L$ are summarized. These are FAN-IN, FAN-OUT, supply current level, Epi-layer doping concentration and wired A-ND property.
An upward current gain is 5 of 1 collector and 2.5 of 4 collector test Tr. The $t_{DHL}$ of toggle flip flop is max. 5㎲ and min. 2.5㎲. The counter operating range of supply voltage through 1.1K ohm injector resistor is from 2v to 11v. At 5v, max. operating frequency of counter is 1.7 MHz of devide by 6, 1.4 MHz of decade. The power dissipation per one chip is max. 51.2mW, min. 1.2mW. By stacking of two chips, 25% of power is saved compared with the conventional method at 5v and 1.1K ohm resistor.
In combination with $I^2L$ seven segment decoder and driver, counter chips are successfully operated as a digital watch.
