As integrated circuits are being used more and more in digital network, module level rather than gate level fault diagnosis is required.
In this thesis, by means of some structural analyses and extended logic concept based on path sensitization technique, a module-level-test-pattern generating package is designed bases on the single fault assumption.
Test pattern obtained can be used for the fault diagnosis of digital networks as a module level.
This procedure can be applied to sequential network as well as combinational network. But, in case of sequential networks, some assumptions should be made. They are; 1) the change in clock can be a part of test input, 2) flip-flops can be resettable to a known state.
This procedure is implemented on NOVA 840 computer, and the performance of the system is demonstrated with some sample logic networks.
