서지주요정보
(A) study on the integrated injection logic-analysis and new fabrication process = Integrated Injection Logic 에 대한 연구 : 해석 및 새로운 제작 방법
서명 / 저자 (A) study on the integrated injection logic-analysis and new fabrication process = Integrated Injection Logic 에 대한 연구 : 해석 및 새로운 제작 방법 / Kwang-Seok Seo.
저자명 Seo, Kwang-Seok ; 서광석
발행사항 [서울 : 한국과학기술원, 1978].
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소장정보

등록번호

4000516

소장위치/청구기호

학술문화관(문화관) 보존서고

MEE 7824

SMS전송

도서상태

이용가능

대출가능

반납예정일

초록정보

Mathematical analyses for the base and the collector currents of the lateral pnp transistor and the vertical npn transistor are described for the conventional $I^2L$ structure. The lateral collector current of the pnp transistor and the high level injection in $I^2L$ gate are described by simple analytical expressions. Each base current component of the inverted npn transistor is discussed physically and quantitatively and determined by experiments. It is shown that the collector area must be maximized and N epitaxial layer width and resistivity must be low to increase the upward npn current gain in $I^2L$. An upward npn current gain of 10, a speed-power product of 2.6 PJ and a minimum propagation delay time of 36 ns have been obtained from the test chip fabricated by the standard $I^2L$ process of 10 um minimum linewidth. A Toggle flip-flop composed of standard $I^2L$ gates, which has a maximum toggle frequency of 3.5 MHz, has been fabricated. A new $I^2L$ fabrication process using spin-on sources is proposed. It may offer a high-performance $I^2L$ structure having a self-aligned npn collector and $p^+$ extrinsic base to increase the upward npn current gain.

서지기타정보

서지기타정보
청구기호 {MEE 7824
형태사항 iii, 80 p. : 삽도 ; 26 cm
언어 영어
일반주기 저자명의 한글표기 : 서광석
지도교수의 영문표기 : Choong-Ki Kim
지도교수의 한글표기 : 김충기
학위논문 학위논문 (석사) - 한국과학기술원 : 전기 및 전자공학과,
서지주기 Reference : p. 76-80
주제 Junction transistors.
Epitaxy.
IIL. --과학기술용어시소러스
접합 트랜지스터. --과학기술용어시소러스
Integrated injection logic.
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