Mathematical analyses for the base and the collector currents of the lateral pnp transistor and the vertical npn transistor are described for the conventional $I^2L$ structure. The lateral collector current of the pnp transistor and the high level injection in $I^2L$ gate are described by simple analytical expressions. Each base current component of the inverted npn transistor is discussed physically and quantitatively and determined by experiments. It is shown that the collector area must be maximized and N epitaxial layer width and resistivity must be low to increase the upward npn current gain in $I^2L$.
An upward npn current gain of 10, a speed-power product of 2.6 PJ and a minimum propagation delay time of 36 ns have been obtained from the test chip fabricated by the standard $I^2L$ process of 10 um minimum linewidth. A Toggle flip-flop composed of standard $I^2L$ gates, which has a maximum toggle frequency of 3.5 MHz, has been fabricated.
A new $I^2L$ fabrication process using spin-on sources is proposed. It may offer a high-performance $I^2L$ structure having a self-aligned npn collector and $p^+$ extrinsic base to increase the upward npn current gain.
