The purpose of this thesis is to design and implement a multiprocessing system in the sense of a central processor and an autonomous I/O processor.
In the mini-to-medium level computer systems, the designer is faced with ever increasing input/output requirements which cannot be accommodated in the traditional way.
Unlike the monoprocessor system where the CPU function of I/O part and the instruction execution part are combined, a multiprocessor system has been designed and studied in order to provide high I/O data rates and I/O capability of wide variety on smaller machines.
In our system, the CPU module which has 16-bit word length is made of intel 3000 series 2-bit slice microprogrammable microprocessor to emulate the PACE, 16-bit microprocessor from National Semi-conductor.
The CPU module is coupled through a shared memory which is used for message and data buffers and some flags with another CPU module based on the 8-bit microprocessor 8080 whose purpose is to serve as an autonomous I/O processor.
The performance test is carried out from various viewpoints and through various method. And some problems that commonly occur in multiprocessing architecture are studied during the design and subsequent test of the system.
The I/O processor and the shared memory subsystem has been debugged with a minor modification necessary to link the above to an 8080 microprocessor based microcomputer system. This was done in order to pursue the debugging of the I/O and 16-bit CPU systems independently and concurrently.
