In the first part of this thesis, the input jitter tolerance in digital muldex equipments has been studied. It is shown that the jitter tolerance at the input ports of digital muldexes is a function of the quality factor of the input timing extraction circuit, elastic buffer sizes of the synchronizer and desynchronizer in the muldex, the frame structure of the muldex, and the characteristics of PLL in desynchronizer. It is also shown that only a limited part of input jitter can be absorbed by the justification process of the multiplexing, and hence the elastic buffer cells must buffer the remained jitter to avoid multiplexing errors.
A design method to determine the buffer sizes for absorption of the remained input jitter has been presented for a given input jitter. It is applied to obtain the minimum buffer size for input jitters allowed by the CCITT recommendation for various transmission bit rates from 6. 3Mbit/s to 139Mbit/s.
In the second part, the timing jitter is obtained in the optical receiver with a PIN-GaAs FET front end, taking into account both thermal noise and flicker noise. It is shown that the flicker noise effects on timing jitter are significant even in the range of several giga bit rates.
The calculated jitters are compared with the measured values at both 70 Mbit/s and 140Mbit/s in a experimental system. It is found that the timing jitters including the fliker noise are quite close to the measured jitters for low input powers.