A new pipe-line analog-to-digital (A/D) converter using charge-coupled device (CCD) is proposed and demonstrated with an experimental 4-bit prototype. The proposed A/D conversion scheme can be easily implemented in monolithic form, due to the advantages of small power consumption and small amount of support circuitry.
The design and realization of the experimental prototype has been performed in two steps. The first step is to fabricate a monolithic chip, 'CCADC', which executes almost all the core operations required for the A/D conversion. The standard p-channel MOS technology was used for the fabrication of the CCADC, with an additional phosphorous implantation for a potential barrier and an aluminum anodization process for an overlapped gate structure. The second step is an implementation of the peripheral circuitry, such as comparators, dump gate control logic and data sequencer, with TTL and CMOS discrete IC's.
The experimental prototype charge-coupled A/D converter was operated in $1^\frac{1}{2}$ phase clocking mode, where the measurement and detection of the signal charge occurs under the quiet DC-biased electrodes. High/low and DC levels of the $1^\frac{1}{2}$ phase clock were adjusted on the basis of the experimental measurement of surface potential vs. gate voltage.
For most sample devices, input signal voltage range was found to be 2.4±0.1 volt which corresponds to a charge magnitude of 7.2±0.3 pc, and DC offset at the input was adjustable between -5 volt and -10 volt by varying the DC bias applied to the input gate(IG) 1.
The nominal value, in charge magnitude, of each bit is 3.6 pC, 1.8 pC, 0.9 pC and 0.45 pC in the order of MSB(Most Significant Bit) to LSB(Least Significant Bit). Design effort was focused on the conservation of the binary ratio of (8:4:2:1) among the areas of four potential wells, whose charge storing capacities correspond to the magnitudes of the corresponding bits. Uniformity measurement of each bit magnitude was carried out for 16 sample devices which showed that all smaples fall within the bit magnitude error of $\frac{1}{2}LSB$(3% of the full scale value).
Nonlinearity error in the A/D conversion was found to be less than $\frac{1}{2}LSB$ for the signal sampling frequency between 20 kHz and 200 kHz. The abnormally high lower limit was due to the dark current density of 10μA/㎠ at room temperature, which is about 1000 times as large as the state-of-the-art value, 10nA/㎠. Dry ice vapor was blown on the CCADC chip during its operation to lower the chip temperature down to 5℃. As a result, the dark current density was reduced to 1.5 μA/㎠ and the lower frequency limit, in this case, was observed to be lower than 1 kHz.
Dynamic characteristics of the charge-coupled A/D converter was extensively studied for various signal waveforms, by incorporating a commercial 4-bit D/A converter to reconstruct the original analog signal and a subtracter for the observation of the quantizing error. The abnormal 'glitch' observed in the reconstructed lowering staircase waveform for a ramp input signal was found to be due to 'dump slot' which is created in the signal charge path depending on the dump gate condition and captures a fraction of the next signal charge.
A novel input scheme called 'slot zero insertion' to circumvent the deleterious effect of the dump slot was devised and adopted as a standard input scheme for the experimental prototype A/D converter. The magnitude of the 'slot zero' charge to completely fill up the dump slot was found to be typically 0.9 pC, 0.7 pC and 0.45 pC for three consecutive dump slot #1, #2, #3 for a potential depth of 1 volt in the dump slot.
By incorporating a novel experimental scheme, the amount of total charge transfer loss on each charge transfer path was separated into two components, one due to the limitation from the free charge transfer mechanism and the other due to the surface state capture.
The measured value of the charge transfer loss due to the surface state capture agrees well with the theoretical value predicted from a model, in which the magnitude of the dark current density and the surface density are key parameters.
Finally, various waveforms due to charging and discharging of the S-well (charge sensing potential well) capacitances were analyzed in terms of the free charge transfer and the current conduction mechanism of the MOS transistors. A gross estimate of the effective electrode length to account for the two-dimensional charge transfer was carried out to yield a quite reasonable figure.
현재 analog신호 처리 분야에서 널리 사용되고 있는 charge coupled device 를 이용하여 새로운 A/D변환기를 제안하고 4 - bit P - channel소자를 실험 제작하였다. 이 A/D변환기의 핵심부분은 CCADC라는 monolithic silicon chip으로 실현하였고, clock발생기를 비롯한 control회로는 discrete IC를 사용하여 주변회로로 제작하였다. CCADC chip은 보통의 P - channel MOS 제작 기술에 다가 overlapping gate구조를 실현하기 위한 aluminum양극 산화 기술과 potential barrier를 실현하기 위한 phosphorus implantation을 추가한 공정으로 제작되었다.
이 A/D변환기의 설계에서는 A/D변환의 정확성에 직접적인 영향을 주는 4개의 potential well (M-well)의 면적비(8: 4:2:1)가 제작과정을 통하여 보존될 수 있도록 주력 하였으며 제작된 sample소자 16개에 대하여 4개의 M-well의 전하용량을 측정해 본 결과 모든 sample에 대하여 모든 M-well의 전하용량의 오차는 $\frac{1}{2}LSB$이내에 들어 있었다.
1차 aluminum과 2차 aluminum전극 아래서의 silicon표면 전위를 측정하여 이에 따라 clock전압을 설계하였다. 측정된 출력전류값으로 부터 입력전압과 입력 전하량의 관계를 산출한 결과 약 3.0m±0.1pC/volt의 값을 얻었다.
Potential well(S-well)에 저장된 신호전하는 floating diffusion과 on-chip MOS transistor로 이루어진 source follower에 의해 감지 하였으며 $1\frac{1}{2} phase clock$을 사용하여 전하의 감지가 DC phase의 clock전극 아래서 행하여 지게 함으로써 매우 안정된 동작을 얻을 수가 있었다.
Analog입력신호에 대한 이 A/D변환기의 동적 특성에서 생기는 glitch의 원인 mechanism인 'dump slot'을 설명하였으며, 이러한 오동작을 방지하기 위한 입력방법인 'slot zero'삽입방법을 사용한 결과 정상적인 A/D 변환 특성을 얻을수 있음을 확인하였다.
제작된 4-bit, p-channel A/D변환기의 최대 throughput rate는 동작 clock주파수의 상한과 같으며 $2×10^5 samples/sec$로 나타났다. 동작 clock주파수의 하한은 약 20kHz로 측정되었는는데, 이것은 비정상적으로 큰 dark current(10μA/㎠) 때문인 것으로 판명되었다. Dry ice증기로 cooling을 하여 동작 온도를 20℃ 만큼 내린 결과 dark current의 크기는 약 $\frac{1}{5}$ 정도로 줄었으며, 이때의 동작 주파수 하한은 1kHz이하로 내려갔다.
제작된 CCADC chip에서의 전하의 이동경로에 따른 총전하 이동 손실량 ($Q_ℓt$)을 자유전하이동 손실량 ($Q_ℓf$)과 surface state에 의한 손실량 ($Q_ℓs$)으로 분리해 낼수 있는 측정방법을 제시하였다. Dark current의 크기와 surface state의 밀도를 parameter로 하여 각 전하이동 경로에 따른 surface state에 의한 손실량 ($Q_ℓs$) 를 계산해 내는 model을 고안하여, 이로부터 계산된 $Q_ℓs$의 계산치를 상기한 측정 방법으로 부터 산출된 값과 비교하여 잘 일치하는 것을 확인하였다.
이 논문에서 제안하는 전하 결합 A/D변환기는 구조가 간단하여 chip면적이 적게 들고, 전력소모가 적으며, pipe line식 A/D변환이 가능한 등의 장점이 있어서, 현재 수요가 급증하고 있는 analog신호처리 소자와 함께 on-chip으로 제작되기에 적합한 소자인 것으로 판단되었다. 끝으로, CCADC chip의 dimension 을 더욱 줄이고, 제작공정을 개선하여 dark current의 밀도를 100nA/㎠ 정도 이하로 줄일 수 있다면 동작 주파수 범위가 0.1kHz - 500kHz 정도 까지는 어렵지 않게 얻어질 수 있을 것으로 기대된다.
