Inner-product implementation of hetero-associative memory and its application to multi-layer bidirectional associative memory (MBAM) is discussed. Although analog calculation is performed in the chip, only binary storages and interfaces are required for binary input and output patterns. The prototype chip is designed in 1.2 micron CMOS technology. It is capable of storing 8 input and output memory patterns of 8 bit each and can perform associative recall in 300 ns per layer. By cascading these chips one may organize MBAM, which is capable of performing complex hetero-association including XOR problem.
