In this thesis, a distributed cache coherence protocol for shared memory multiprocessors with multistage interconnection network is proposed.
There are some related works in the cache coherence protocol for the multi-stage interconnection network. Some have good performance, but have heavy memory overhead. Others have poor performance, but have light memory overhead. With heavy memory overhead, it is too expensive to implement. So we propose a new protocol with light memory overhead but performance is not degrade significantly.
In this proposed cache coherence protocol, directory is maintained as a binary tree form. We can reduce memory overhead, increase scalability, but performance is not degrade significantly. We compare this protocol with others by analytical modeling using Markov chain and trace driven simulation and shows reasonable performance.
