In recent years, as density of integrated circuit increases, it is changing quickly from two-dimensional to three-dimensional. A major current focus in three-dimensional integrated circuit (3D IC) is how to connect chips vertically. Among vertical interconnection technologies such as bond wire, flip chip, and through silicon via (TSV), the TSV is a remarkable technology to achieve a high level in not only the degree of integration but also electrical performance. Moreover, as digital systems speed gets higher, the timing margin becomes much tighter. Then, the clock signal which is a timing reference for the operation of systems critically affects to the performance of synchronous digital systems. That is, it is important for the clock signal to be distributed with low skew and low jitter. Much research has focused on low skew and low jitter clock distribution network (CDN) in two-dimensional integrated circuits. However the CDN in TSV-based 3D IC has not been studied yet, thus the 3D CDN in TSV-based 3D IC is strongly needed.
In addition, low power consumption technology is major issue in semiconductor industry. However the amount of consumed power due to clock signal severely increases as the operating frequency increases. That is, the power consumption is also critical to system performance. The technology of 3D IC is developed due to the high density. That is, the reduction of the area consumption is becoming important in 3D IC. The interconnection metal for using the transmission of the clock signal occupies a lot portion of the on-chip area, so minimizing area consumption of CDN affects the whole area consumption. Thus, as systems become smaller and have more functions, it takes considerable effort to reduce the size of the CDN. For this reason, area consumption is also needed as the performance evaluation factor of CDN. Hence, new 3D CDN schemes for TSV-based 3D IC are proposed by considering skew, jitter, power consumption and area con-sumption.
The 3-types of proposed 3D CDNs are centered single TSV 3D CDN (CST 3D CDN), distributed multi TSV 3D CDN (DMT 3D CDN) and vertical TSV tree 3D CDN (VTT 3D CDN). In the CST 3D CDN, each DRAM is connected by a TSV at the center, and in the DMT 3D CDN, it is connected by many TSVs at edge. Finally, the clock signal is transmitted from GPU to DRAM through TSV composed of vertical tree shape in the VTT 3D CDN. The performances of these 3D CDNs are simulated and analysis according to temperature variation. In addition, the 3-types of 3D CDN are compared in each performance factor such as skew, jitter, power consumption and area consumption.
시스템의 고속화가 요구되어짐에 따라 디지털 신호의 전송 속도가 빠르게 증가하여 메모리를 보다 높은 주파수에서 동작시키는 기술이 나날이 발전하고 있다. 따라서 신호 전송을 제어하는 클락 신호의 동기화의 중요성은 항상 이슈가 되어왔다. 뿐만 아니라, 소형화 추세에 따라 3차원 반도체 집적 기술이 등장하게 되었다. 그 중 한가지로 관통 실리콘 비아(Through Silicon Via: TSV) 기술이 등장하였으며, 이 집적 기술은 실리콘 내부를 관통하는 원통형 비아를 삽입함으로써 다이간의 통신 거리를 줄이고 파워를 절약할 수 있게 되었다. 여러 장점들에도 불구하고 신호 무결성(signal integrity), 전력 무결성(power integrity), 열 무결성(thermal integrity) 등 여러 가지 해결해야할 문제들이 여전히 존재하며, 3차원 반도체의 특성 상 실제 칩이 적층되면 실리콘 다이간 언더필이나 SiO2와 같이 전기적 부도체 물질을 삽입으로 인해 열 방출을 방해하는 요소로 작용하게 된다. 즉 칩의 온도 상승으로 인해 클락 신호 전달에 영향을 미치게 된다.
본 연구에서는 3차원 반도체 집적회로에서 전원 잡음(power supply noise) 및 실리콘 다이가 적층됨으로써 발생하는 열이 클락 신호 전달에 미치는 영향을 분석하고, 관통 실리콘 비아를 삽입한 3차원 반도체 집적회로에서 3가지 클락 분배망을 제안하고 각 클락 분배망 구조에 따른 스큐(skew)와 지터(jitter), 전력 소모 및 면적 소모를 비교 분석한다.
