In silicon integrated circuit technology, ferroelectric thin films have been importantly studied since they are the most promising materials for future non-volatile memory devices. PbTiO3 (PTO) is the one of the most suitable material for non-volatile memory devices, because it has the highest spontaneous polarization (Ps) value. The subject of size effect on ferroelecticity has been of highest interest for many years to overcome the limit of memory density. As the ferroelectric film thickness decrease, it is possible to make small domain size of penetrating the film thickness direction, which is more stable than one of half penetrating in the probe-based data storage.
To make thin and smooth PTO films, Pt / Zr bilayers were deposited by dc-magnetron sputtering. The surface roughness of Pt layer was controlled by different pressure, power and temperature, and thin film stress analysis was simultaneously held to investigate how these process parameter affect on the surface roughness. After optimizing the Pt layer deposition condition, TiO2 was deposited on the Pt, and PbO gas phase reaction was carried out. TiO2 seed layer increase the number of active sites for PTO nucleation and, hence, allows crystallization of perovskite phase rather than nonferroelectric pyrochlore phases. The d33 hysteresis loop and PFM (piezoelectric force microscope) images were obtained and these results confirmed the ferroelecticity of PTO films. The hysteresis loop is shifted toward negative bias. Many defects exist at grain boundaries and the interface between ferroelectric film and the electrode because of lattice mismatching, vacancies, etc. Since these defects are charged, ferroelectric domain may be balanced and stabilized by them and cannot be switched easily. Besides these charges, built in potential would be developed at the interface between ferroelectric film and metal electrode because of the work function difference, and it contributed on the polarization imprint.
Thin and smooth PTO films successfully deposited using the gas phase reaction sputtering, and this method suggest us the possibility for high-density memory device.
가스상 반응 스퍼터링 방법을 이용하여, Si 상부에서 20 nm 두께의 평활 한 PbTiO3 (PTO) 박막을 제조하였다. 본 박막의 증착을 위해서, 우선 Pt / Zr 박막을 dc-magnetron 스퍼터링 방법을 이용하여 증착 하였다. 이 때 낮은 표면 평활도를 갖는 Pt 하부 전극 층을 제조하기 위해 증착 압력과 파워 그리고 온도를 변화시켜 주었으며, 박막에 걸리는 응력을 분석하여 응력과 표면 평활도의 관계를 살펴보았다. 이렇게 제조된 Pt 박막의 상부에 8 nm 두께의 TiO2 seed layer을 증착하고, PbO 가스 반응 스퍼터링을 통하여 20 nm 두께의 PTO 박막을 제조하였다. Piezoelectric force microscopy를 이용한 domain 관찰과 piezoresponse hysteresis loop 측정을 통하여 강유전체 박막이 형성되었음을 확인할 수 있었다. 특히 hysteresis loop가 negative bias쪽으로 shift된 polarization imprint현상을 확인할 수 있었다. 이러한 연구 결과로부터, 가스상 반응 스퍼터링을 이용하여 얇고 평활 한 20 nm 두께의 PTO 박막이 성공적으로 증착 되었으며, 이는 향후 메모리 소자의 저장 밀도 향상의 가능성을 제시하였다.
