Recently, The CMOS Image Sensor(CIS) is used in a variety of applications due to its several advantages such as low power consumption, random access, scalability of architecture and compatibility with CMOS circuitry. The important performance factors of the CIS which determine the image sensor performance quality are Fixed Pattern Noise(FPN), sensitivity, dynamic range. To achieve the high sensitivity and wide dynamic range performance, The Self-adaptive active pixel structure has been previously reported. The Self-adaptive APS(SAPS) benefits from the improved performances of high sensitivity, wide dynamic range, low power, and low cost.
However, the FPN arising from the non-uniformity caused by the parameter variations in the SAPS has been still one of the essential issues to be improved. The FPN in general appears as a time-invariant, fixed, and spatial pattern on the image, degrading the image quality. If the FPN is not suppressed sufficiently, the non-uniformity is seen as a “snow-like” shade over the image. So, reducing the FPN is required to enhance the signal-to-noise ratio and also the dynamic range.
In the SAPS, one of the most critical parameters in the FPN is a threshold voltage variation of the reset transistor. This variation, resulting from the fabrication process, introduces an offset in the signal of each pixel. These offsets give rise to the FPN. The implementation of Correlated Double Sampling(CDS), which is the conventional approach to reduce the FPN on SAPS, cannot eliminate the FPN caused by the device mismatch of the reset transistor. To reduce the effect of the device mismatch in the reset transistors, a new hard-reset mode of SAPS is proposed and the operation of the proposed APS is theoretically analyzed and confirmed using a Monte carlo simulation. The prototype chip is fabricated using a Magnachip 0.18um CMOS logic process to evaluate the proposed pixel sensor. The measured FPN of the proposed new SAPS is found to be reduced by 67% compared to that of the previously reported SAPS. In addition, with an optimized layout design, the dynamic range(DR) of the PMOS hard-reset SAPS has been improved to be 83dB, with an increase of 10dB compared to that of the previous SAPS structure.
Consequently, the new proposed pixel is found to allow improvement in the FPN, dynamic range, sensitivity. The results demonstrate that the proposed pixel is promising for high-performance CMOS active pixel-sensor applications.
최근에 CMOS Image Sensor(CIS) 는 다양한 분야에 이용되고 있다. CIS에서 중요한 factor로는 dynamic range, sensitivity, Fixed Pattern Noise등이 있으며 본 연구실에서는 높은 sensitivity와 넓은 dynamic range를 가지는 픽셀에대한 연구로 Self-adaptive APS를 개발하였다. 하지만 위의 픽셀에는 동작 방법의 특성상 capacitance가 중간에 커지기 때문에 문턱전압의 영향이 reset 과 signal의 출력시에 달라지게 되어 높은 FPN이 나타나게되는 단점이 있다. 이와같은 높은 FPN이 나타나는 주요한 원인으로 reset 트랜지스터의 문턱전압 variation이 있으며 본 연구에서는 reset 트랜지스터 문턱전압의 variation을 줄여 최종적으로 Self-adaptive APS에서 낮은 FPN을 구현하는데 목표가 있다. SAPS에서 높은 FPN이 나타나는 주요한 원인을 Cadence Monte carlo simulaion을 통해 검증하였으며, Hard-reset mode를 이용하는 SAPS를 제안하고 simulation 검증 후, Magnachip 0.18um CMOS logic process를 통해 픽셀을 array로 제작하여 최종적인 FPN값을 추출하였다. 그 결과 기존 SAPS보다 67% 감소한 7 mV 정도의 FPN을 얻을 수 있었다. 이와같은 연구를 통하여 약한 빛에서는 높은 sensitivity를 가지며 강한 빛에서는 넓은 dynamic range를 갖고 낮은 FPN을 갖는 픽셀을 구현할 수 있었다.
