In the context of technology scales down and processing speed increases, the electrical interconnections are considered as the bottle-neck of the high-speed signal transmission between chips, especially the large data width transmission between CPU (Central Processor Unit) and memories in computer systems. The optical links have merged as one of the promising solutions for replacing the electrical interconnections.
The large data width of signal transmission from CPU-to-memories is in the order of more than 64 data buses, 12 address buses, and some clock/strobe or control signal buses; the speed of signal transmission on these buses is around 400 Mb/s to 1.2 Gb/s. As the CPU processing speed increases higher, the electrical link can not support the signal transmission. Meanwhile, the optical link can operate up to 5-10 Gb/s at this moment, so the Serializer and Deserializer to convert low speed parallel data to high speed serial data and vice versa are really needed to make the optical link more efficiently. The other problem is that the data width is not often power to 2.
In this thesis, a bidirectional Serializer/Deserializer for chip-to-chip optical interconnection is designed. This Serializer/Deserializer can satisfy both condition of high speed operation and various number of input/output channel as owing the combination architecture of shift-register and tree Multiplexer/Demultiplexer. The proposed chip can operate up to 10 Gb/s with 18 differential input/ouput channels. The sharing common block between Serializer and Deserializer allows us to save the power consumption of 63% and 37% in Multiplexer/Demultiplexer modes respectively compared to using separate chips for the two modes, and also estimated chip area reduction is about 25%. Integration bidirectional Serializer/Deserializer with TRx is also discussed and simulated. The bidirectional Serializer/Deserializer integrated with TRx can operate up to 5 Gb/s.
