This thesis reviews and analyzes four reported low noise amplifier (LNA) design techniques applied to the cascode topology based on CMOS technology: classical noise matching (CNM), simultaneous noise and input matching (SNIM), power-constrained noise optimization (PCNO), and power-constrained simultaneous noise and input matching (PCSNIM) techniques. Very simple and insightful sets of noise parameter expressions are newly introduced for the SNIM and PCSNIM techniques. Based on the noise parameter equations, this work provides clear understanding of the design principles, the fundamental limitations, and the advantages of the four reported LNA design techniques so that the designers can get the overall LNA design perspective. As a demonstration for the proposed design principle of the PCSNIM technique, a very low power folded-cascode LNA is implemented based on 0.25 $\mum$ CMOS technology for 900 MHz applications. Measurement results show the noise figure of 1.35 dB, power gain of 12 dB, and IIP3 of -4 dBm while dissipating 1.6 mA from 1.25 V supply (0.7 mA for the input NMOS transistor only). The overall behavior of the implemented LNA shows good agreement with theoretical predictions.
The most commonly used receiver architecture is the superheterodyne. However, in a monolithic implementation, image cancellation is difficult due to the limitation of on-chip filter. The use of image rejection architecture alleviates this problem to some extent. To augment the amount of image rejection beyond what is practically achieved by the image rejection architecture, a tracking notch filter is integrated with the low noise amplifier. The proposed IR-LNA is optimized for 5.25 GHz WLAN with IF frequency of 500 MHz applications. The measurement results show power gain of 20.5 dB, lower than 1.5 dB NF, and image rejection of 26 dB, Two-tone test results indicate -5 dBm and -8 dBm of IIP3 for the case of using and not using the notch filter, respectively. The circuit operates at supply voltage of 3 V, and dissipates 4 mA in 0.18 $\mum$ CMOS technology.
