The fundamental ideas of Software Defined Radio are the flexibility in design for various communication needs by utilizing digital signal processing technology. Software Defined Radio is emerging as potential pragmatic solution for the current and next generation wireless multimedia communication systems. In this thesis, the design of digital up and down converter for reconfigurable WCDMA system is presented, using Digital IF technology which is one of the basic components.
In actual implementation, main consideration is given to efficiently that can lead to obtain the lower power consumption, and the smaller space requirement within FPGA chips. Numerically controlled frequency oscillator and multi-stage filters are designed to show the efficiency and especially for filter design. The novel technique, based on the use of canonic signal digit (CSD) code, is applied to implement the anti-alias filter structures. Simulation results are parts of the actual implementation with VHDL is shown to reflect the effects of theses research.
본 논문에서는 Software Defined Radio의 개념을 이해하고 Digital IF 기술을 이용하여 재구성 가능한 WCDMA System에서의 저전력의 Digital Up-Down Converter구조를 제안하였다. 제안되어진 재구성 가능한 WCDMA System을 SystemView를 이용하여 부동 소수점 모델로 구축하고 시뮬레이션 결과를 나타내었다. 그리고 제안되어진 Digital Up-Converter와 Digital Down-Converter를 구현하기 위해 최적화 설계기법을 이용하여 Direct Digital Synthesizer와 Multi-stage filters를 저전력과 감소된 복잡도의 관점에서 VHDL로 설계하고 FPGA에 구현하여 성능을 분석하였다.
