We proposed a silicon flip-chip module with a self-aligned structure capable of the passive alignment for the optical coupling, and 3-D packaging integrated with through-wafer via interconnections and the buried structure of fiber and photo-detector. The fiber and the photo-detector are buried in the grooves of silicon substrate face-to-face through the wafer window. And the other chips are integrated on the surface of the substrate and the through-wafer via interconnection can be used as a short signal path and the platform for the flip-chip bonding. It can be extended to the 3-D packing of ICs easily.
We presented detailed fabrication process of the through-wafer via interconnection and high frequency characerization of a low pass filter module flip chip bonded to the coplanar waveguide line with via interconnects. 25㎛ thick oxide layer on low resistivity-5 ohm·cm silicon wafer was fabricated by the silicon anodization and the thermal wet oxidation at 1060℃. and 240㎛ long through-hole vias are filled with the copper barrels electro-plated within the thick oxide side wall. A RF LPF chip was flip-chip bonded directly to the top side of vias. The evaluated cutoff frequency of this LPF module was 2.143GHz and other performance characteristics are discussed.
An optical receiver module was fabricated with the through-wafer via interconnection. 3-dimensional packing of the fiber, photo-detector, and transimpedance amplifier(TIA) chips was assembled and we evaluate the performance of optical module. The modulated 167KHz 1300 nm light is detected and amplified. The optical loss was 0.5dB excluding fiber originated loss and the transimpedance gain of TIA was 1.44kohm with one output of open connection. It shows the good possibility of the 3-D packaging of opto-electronic interconnects.
A V-grooved waveguide on the thick oxide (TO) layer with the polymer core structure is proposed and fabricated for the passive alignment of the assembly of the silicon optical bench(SiOB). The characteristics of the oxidized porous silicon(OPS) process on the V-groove etched silicon wafer were analyzed for the design of the method for the robust passive alignment of SiOB. The changes of the widths of V-groove pattern during OPS process were inspected with the split run of anodization current. The higher current resulted in the more broad and deep waveguides, and the smaller inner angle is formed between the triangular walls of the cladding. Samples with the mere dielectric reflector was saw-cutted at the optical launching port and measured. With the HeNe laser the wave-guiding was observed and the overall loss was measured as of 20dB. This poor loss seems to be due to the rough surface saw-cut. The methods to improve the performance were discussed.
3차원 적층 패키징과 수동 광결합이 가능한 실리콘 광모듈을 제안하여 그 시작품을 만들어 측정을 하였다. 웨이퍼 관통형 비아 연결을 가지고, 광섬유와 포토다이오우드가 실리콘 식각 홈에 매몰되는 구조를 구현하여서 신호처리 칩등의 다층 및 양면 집적이 가능하게 만들었다.
양극산화 및 1060℃ 열산화기법에 의하여 저저항 p형 실리콘 기판에 고저항 이산화규소의 다공성 후막을 웨이퍼 표면과 웨이퍼 관통형 비아의 측면에 동시에 각각 25㎛, 10-20㎛ 두께로 만들어 RF 신호 절연에 충분한 산화막을 만들었다. 지름 80㎛, 길이 220㎛ 의 웨이퍼 관통 비아를 구리 도금으로 채워서 배선 연결을 하였고, 웨이퍼의 양면에 Au 배선을 도금 방식으로 형성하여, Coplanar waveguide(CPW) 과 플립칩 본딩용 패드를 설정한 다음, 저역통과필터를 조립하여 특성을 측정하였다. 모델링 결과 비아의 주 등가회로는 0.056 ohm + 0.079 nH 로 추출되어 매우 양호한 결과를 얻었다. 조립된 저역통과필터는 차단주파수가 2.143GHz 로 칩상태의 경우보다 약 0.2GHz 열화되었다. 이는 모사실험 결과 CPW와 비아 연결 부위의 오정렬로 인한 것으로 판명되었다.
같은 형태의 기판의 양면에 광섬유와 광검출용 다이오우드 거치용 홈을 KOH 용액에서 실리콘 이방성 습식 식각으로 만들고, 노출된 이산화규소 다공성 후막을 완충불산용액으로 식각하였다. 만들어진 기판에 광섬유, 포토다이오우드, 임피던스 변환증폭기(TIA)를 집적하였고, 보드에 장착한 다음에 광특성을 측정 하였다. 광섬유 손실을 제외한 결합손실은 0.5 dB, TIA 증폭률은 1.44 Kohm 이었다.
