For the design of communications circuits, the ultimate goal is to implement a single chip transceiver with the minimum number of off-chip components. A high level of integration enables significant cost and size reduction. However, for a cost-effective CMOS process, one of the most challenging parts of transceiver integration is the realization of low phase noise synthesizers with low-Q on-chip components. One approach overcoming the limitation is to use an LC-tank voltage controlled oscillator (VCO) with a Q-enhancing technique for the inductor [1]. Another approach is to use a delay-locked loop (DLL) and a frequency multiplier with an edge combiner [2]. The phase noise is improved because no timing jitter is accumulated from cycle to cycle when DLLs are used. However, the number of delay cells determines the multiplication factor and the multiplication factor is
fixed. Consequently, the latter method has limitations whenever a variable or a large multiplication factor is required.
This paper presents a DLL-based frequency synthesizer that selectively reuses a delay cell. By switching the number of delay cells that a signal goes through in a proper sequence, the frequency synthesizer can generate multiple frequency output with a small number of delay cells. With only 9 delay cells, the test chip achieves frequency multiplication factors greater than 240. It also provides multiple frequency output by adjusting the multiplication factor similarly to a conventional frequency synthesizer.
This work describes a 2.4 GHz frequency synthesizer based on a delay-locked loop
(DLL). Because the proposed frequency synthesizer is basically developed from a DLL, it has no jitter accumulation thereby resulting in a low close-in phase noise of -105 dBc/Hz. Although only 9 delay cells are used, the proposed delay cell reusing scheme realizes frequency multiplication factors greater than 240 and provides multiple frequency output with the resolution of phase detector (PD) comparison frequency. This architecture has been verified by implementing the synthesizer in a 0.18 μm CMOS technology.
본 논문은 지연셀을 선택적으로 재사용하는 지연동기회로를 기반으로 한 주파수 합성기를 제안하고 있다. 지연선안에서의 신호의 흐름을 조정할 수 있는 스위치를 두고, 스위칭 순서를 적절히 조절함으로써 적은 수의 지연셀만을 가지고 여러 주파수의 출력을 얻어낼 수 있다. 또한, 제안된 주파수 합성기는 지연동기회로를 기반으로 하였기 때문에 시간잡음이 축적되지 않아 낮은 close-in 위상잡음특성을 보여준다.
측정결과 -105 dBc/Hz의 close-in 위상잡음을 측정할 수 있었다. 이는 기존의 주파수 합성기에 비하여 낮은 수치이다. 또한 9개의 지연셀과 10 MHz의 입력 신호로부터 2.4 GHz의 출력 신호를 얻을 수 있었고, 10 MHz간격으로 출력주파수를 조절할 수 있었다.
이 구조는 CMOS공정을 이용하여 제작되어 증명되었다.
