Recently, flip chip technology has begun to be applied to portable equipment such as cellular phone, PDA, and notebook PCs where improvements in terms of miniaturization and performance have become increasingly important. An advantage of flip chip technology with bumps is that it is generally used to reduce the interconnection length and inductance for very high frequency because the bumps directly connect each terminal. Also by using flip chip technology as a chip mounting technique, the silicon die is directly connected on the substrate without a volume consuming package. This technique is Flip Chip on Board (FCOB) which refers to the connection of unpackaged ICs directly to an organic printed circuit board (PCB). To achieve FCOB, solder bumps should be formed on the I/O pad of IC. However, in the case of very small-size IC, the solder bumps on IC can be damaged during dicing process. Also, it is difficult to apply bumping processes to optical devices such as VCSEL, laser diode because these devices are much smaller than ICs and fragile.
In this study, we have tried the formation of solder bumps on PCB using dry film photoresist (DFR) to overcome the difficulties mentioned above. Because DFRs can be laminated on several substrates with various contour shapes and have planarization effects over holes and irregular patterns of PCB. First of all, to find out the optimum condition of DFR lamination on polytetrafluoroethylene (PTFE/Teflon$＼circledr$) PCB, DFR lamination test varying lamination temperature and speed was performed. PTFE PCB was chosen for the reason of low dielectric loss at high frequency applications. It was found that the optimum DFR lamination condition was lamination temperature of 150 ℃ and lamination speed of about 0.63 cm/s. The major factor for the conformation between DFR and PTFE PCB was lamination temperature. The opening patterns had minimum diameter of 50 ㎛ and pitch of 100 ㎛. Through UV exposure and development of laminated DFR on PTFE PCB, we made opening patterns for indium solder deposition. Indium has low melting point of 156.7 ℃ and it can prevent PTFE PCB from warpage by overheating. Indium solders were deposited on the DFR laminated PTFE PCB by thermal evaporation method. After indium deposition, two different ways of reflow processes were performed. The one was reflow process done after stripping DFR (SR process) and the other was reflow process done before stripping DFR (RS process). The indium solder bumps by RS process were superior to those by SR process in height, uniformity of height, surface roughness, bump shape, and ball shear strength. It is inferred that the reason of the difference between indium solder bumps by two different methods is additional indium inflow during reflow process in the case of RS process.
Flip chip interconnection is becoming popular for packaging of microwave applications. And applying coplanar structures to the development of flip chip technology is very advantageous for realizing low cost microwave applications. So we designed a substrate and a dummy chip which have geometry of conductor-backed coplanar waveguide (CPW) for the microwave frequency measurement. Using the RS process, indium solder bumps were formed on the substrate and dummy chip was flip chip bonded on the substrate. For measurement of properties in microwave frequency range, we measured S-parameter of substrate, dummy chip, and the FCOB structure. Subsequently was extracted the lumped component model of indium solder bump interconnection. As a result of microwave frequency measurement, there was no significant signal loss by substrate and dummy chip. The FCOB structure showed maximum signal loss of 7.5 dB near 14 GHz. Also, there was no significant signal loss at indium solder bump interconnection.
