As the CMOS volatile memory (SRAM or DRAM) technology is improved, many types of high-density memory cell repair methods have been introduced. These are laser fusing, electrical poly fusing, ONO antifuse, CMOS antifuse and so on.
Poly and metal fusing with laser instruments have widely been used in most of the memory manufacturers'. These, however, are not only very expensive, but have a limitation that they can only be done on wafer test, and that they are impossible to use at final test after packaging. Antifuse based on anti-fusing thin oxide between two electrodes has more reliable pre-/post-breakdown characteristics and has been adopted successfully in some commercial circuits, that is, the via antifuse used in the field programmable gate array (FPGA) from Actel, and the oxide-nitride-oxide (ONO) antifuse in DRAM from Hynix. But they are not directly applicable to standard CMOS products because of their incompatibility with standard CMOS process technology.
In this thesis, I propose novel CMOS antifuse one-time programmable (OTP) ROM structure which is fully compatible with standard CMOS process and its application circuit, named, the 3-transistor cell CMOS OTP ROM array. The 3-T cell CMOS OTP ROM array is composed of only three nMOS's. They are an nMOS antifuse, a high-voltage blocking nMOS and a cell access transistor. And this cell occupies very small chip area per 1-bit $(<10＼mu^2 ＼MVAT ANAM 0.18＼mu technology)$. The CMOS OTP ROM array using the antifuse based on permanent breakdown of MOSFET gate oxide is fabricated and characterized with several standard CMOS processes such as TSMC 0.18㎛, ANAM 0.18㎛ and ANAM 0.25㎛ process technologies. Most of all, the 64-kb OTP ROM, which is fabricated with ANAM 0.18㎛ process, its measurement results show that the 3-T OTP ROM structure is well applicable to high-density embedded program ROM for micro-controller units, one-time programmable configuration memory for FPGA, and several types of embedded memory for general or special purpose digital logics. The experimental results show that the proposed structures can also be a viable technology option as a high-density OTP ROM array for modern analog circuits as well as digital program ROMs. The CMOS OTP ROM can also be used for many other analog circuit applications such as CMOS RF circuits, CMOS OP Amps, and ADCs and DACs requiring on-chip trimming ROMs to compensate for the process variations, device mismatches and so on.
The single poly CMOS EEPROM, which uses the gate tunneling phenomenon during programming and erasing, is very useful non-volatile memory for CMOS embedded system because of its multiple times of re-programmable property and its compatibility with standard CMOS process. In this thesis, I propose the structure of novel single-poly CMOS EEPROM, which is programmed and erased with Fowler-Nordheim tunneling phenomenon, and measure the important properties of threshold voltage changes with ANAM 0.35㎛ technology, that is, the I/O cell process of ANAM 0.18㎛ technology.
