The CdTe solar cell is a leading candidate of low-cost thin film solar cells with the cell efficiency of 16.5%. Major problems in CdTe cells are the high contact resistance and the fast efficiency degradation, which can be originated either from the poor CdS/CdTe interface or from the poor CdTe/metal contact under high temperature and/or under illumination.
We have utilized a $Cu_{2}Te$ layer as a Cu source for $p^+$ doping and as a back electrode and have investigated the structural evolution at the $CdTe/Cu_{2}Te$ interface with various annealing temperatures and its effect on the photovoltaic properties in CdTe cells.
The CdTe cell in our study consists of $glass/ITO/CdS/CdTe/Cu_{2}Te/Au$ layers and was fabricated by the following process. A 180-nm thick CdS film was grown on an ITO-coated Corning glass substrate in a thiourea solution at 75℃. A 6-㎛ thick CdTe film was deposited on the CdS film by close spaced sublimation with screen-printed CdTe layer as a CdTe source. The source temperatures and substrate temperature were 650℃ and 580℃, respectively. The stoichiometry and resistivity of the deposited CdTe film were $Cd_{0.97}Te$ and $4 × 10^4 Ωㆍ㎠$, respectively. The samples were annealed at 420℃ with $CdCl_{2}$. Then, a 60-nm thick $Cu_{2}Te$ ayer was deposited on the CdTe film at room temperature by evaporating $Cu_{2}Te$ powder. The samples were annealed at various temperatures for 10 min in $N_{2}$. Then, a 500-nm thick Au was deposited on the $Cu_{2}Te$ layer.
$Cu_{2}Te$ has been applied as a Cu source and as a primary electrode for p+ CdTe back contact. An amorphous interlayer was found at the CdTe/$Cu_{2}Te$ interface by depositing at room temperature and disappeared by annealing at 200℃. Both orthorhombic and hexagonal $Cu_{2}Te$ phases were formed at room temperature and more hexagonal phase was formed by annealing above 200℃ because the hexagonal phase has a better lattice match with CdTe. The series resistance of CdTe cell was minimum of 0.5 Ωㆍ ㎠at 180℃ annealing and the highest cell efficiency of 14% in the area of 0.5 ㎠ was achieved with Jsc=23 ㎃/ ㎠, Voc=0.83 V, and FF=0.72. And the contact between $Cu_{2}Te$ and CdTe was stable compared to carbon contact or other Cu-related back contact which had been reported.
Since the CdTe/metal back contact is stable it is possible to further identify the degradation mechanism of CdTe cells originated from CdS/CdTe junction. The efficiency of the CdTe cell was degraded under light illumination or under thermal stress at 60℃ in $N_{2}$. The degraded cell was partially recovered by applying reverse bias. To analyze the origin of the degradation, photoluminescence spectra and quantum efficiency spectra were measured. The degradation of CdTe cell was caused by the Cu diffusion from back contact to CdS/CdTe junction. The Cd vacancy sites in CdTe layer which are due to the Cd-deficient composition in our study are easily occupied by Cu diffusion, resulting enhanced Cu diffusion. Moreover the diffused Cu atoms through CdTe layer were segregated in the CdS layer and the defect energy level of Cu in CdS was 1.55 eV above which the light transmittance is strongly reduced, reducing the cell efficiency. And degraded efficiency was recovered by reverse bias because the Cu in CdS or CdS/CdTe interface moved to CdTe layer by internal field from the reverse bias.
Based of above the results, it seems that the cell stability as well as the cell efficiency critically depended on the Cu diffusion to CdS layer through Cd vacancy in CdTe. It is very important to minimize the Cd vacancy concentration near the CdS/CdTe interface so that the diffusion of Cu to interface can be avoided. To reduce Cd vacancy in CdTe and CdS, it is necessary to make Cd-rich composition at the CdS/CdTe interface. To make Cd rich composition we deposited very thin Cd layer on CdS film using electrochemical method. The Cd deposition on CdS restricted inter-diffusion of Te and S so that the morphology of CdS/CdTe interface was improved and the $CdTe_{1-x}S_{x}$ mixing layer was minimized. As a result, the Jsc of CdTe cell was greatly improved. We obtained a 13.3% efficiency with Voc=0.79 V, Jsc=24.1 ㎃ ㎠, and FF = 0.7. The depletion width of CdTe cell with Cd deposition increased compared to that of non-Cd deposited CdTe cell and shifted to CdTe layer from EBIC analysis. It suggests that the Cd-rich CdTe at the CdS/CdTe interface make th CdTe layer more i-type or n-type. The CdS/CdTe junction can be either heterojunction or buried homojunction, depending on the amount of Cd composition on CdS layer.
