In the modern digital systems, most of the electromagnetic interference (EMI) from the system is caused by the high-speed digital clock signal. As a method to reduce the EMI from the system clock, the spread spectrum clock (SSC) technique that modulates the system clock frequency had been introduced. The conventional spread spectrum clock generator with phase locked loop (SSCG with PLL) is implemented by controlling the period jitter. Because of the random period jitter of the phase locked loop, the attenuation of the EMI decreases and the implementation is very difficult at the higher clock frequency near the GHz. In this paper, a spread spectrum clock generator with delay cell array (SSCG with DCA) is proposed. The proposed SSCG with triangular modulation profile is implemented by controlling the positions of transition edges using a delay cell array (DCA). The proposed SSCG with DCA that has more attenuation of the EMI and is easily implemented than the conventional SSCG with PLL was demonstrated by numerical simulation. The proposed SSCG with DCA was implemented to IC chip using a $0.35\mu m$ CMOS process and was measured 9dB attenuation of the EMI at 390MHz.
