Error correction codes are used widely in storage systems to reduce errors. Reed-Solomon codes are among the most widely used one because they are capable of correcting burst errors as well as random errors. Reed-Solomon Product-Code, which forms a rectangular array of RS codes on rows and columns, is used for DVD applications. In RS-PC decoding, we should decode RS-PC several times for higher accuracy. But as the decoding times increase, the computation and memory reference also increase.
In this paper, we have presented a low-power scheme for RS-PC decoding and estimated the power in various conditions. To reduce power consumption, we put two small additional memories for dirty bits, which represent whether each row or column is changed or not. The power consumption was simulated by the standard cells database of UMC 0.25$\mu$m and the toggle information of the gate-level Verilog HDL. The power-saving rate varies significantly according to the BER. But the iteration of row and column RS decoding significantly reduces errors, with few errors left. Therefore, we can expect power reduction in most cases.
As a result, we can reduce the power consumption of Reed-Solomon Product-Code decoding at the cost of a small additional area.
