In this paper several methods to use eDRAM (embedded DRAM, on-chip DRAM) in packet switches are analyzed. A practical method using eDRAM as an output queue is proposed especially in a shared bus packet switch. In the newly proposed output buffer architecture, hierarchical output buffer (HOB), SRAM plays a role of the small FIFO buffer between a high-speed shared bus and a large eDRAM output buffer. The high density of eDRAM can provide larger capacity than static memories, which results in lower packet loss probability. This paper shows the performance analysis on the proposed HOB switch of 8 ports with the port speed of 10Gbps for 10 Gigabit Ethernet or OC-192c standards. We determine two optimal configurations of hierarchical output buffer by simulation. One is focused on area reduction issue and the other on reduction of cell loss probability. First one achieve the cell loss probability of $10^{-6}$ and second one does that of $10^{-8}$ at 90% offered load under real trace traffic of IP packets. About 2 times area reduction is obtained by using hierarchical and hybrid output buffer rather than SRAM buffer. A prototype chip has been designed and implemented by using 0.16um DRAM-based SoC technology. During the chip implementation, Both-Side I/O scheme is proposed to double the I/O data bits of eDRAM. The die area is 4mm × 9mm including input generation block. This chip has taped out in May 2002, and is under fabrication up to now.
10Gbps port용 shared bus switch에서의 Embedded DRAM을 이용한 output buffer 구조가 제안되고 구현되었다. 제안된 Hybrid Output Buffer와 Hierarchical Output Buffer는 SRAM과 DRAM을 혼용하여 output buffer에서 필요로 하는 bandwidth를 만족시킨다. DRAM의 높은 집적도로 인해 SRAM에 비해 많은 Buffer 용량을 제공함으로서 결과적으로 Packet Loss Rate를 떨어뜨리는 효과가 있다. 이 Hierarchical Output Buffer구조에서 Uniform Random Traffic과 Internet Real Packet Trace Traffic을 입력으로 가하여 원하는 Packet Loss Rate를 위해 필요로 하는 Buffer Size와 Cell Latency에 대해 Simulation하였다. 그 결과, 90% Offered Load의 Uniform Random Traffic에서는 $10^{-8}$ 보다 낮은 Cell Loss Rate를 갖고, Packet Trace Traffic에서는 $10^{-6}$ 의 Cell Loss Rate를 갖는다. 또한 이 구조를 사용함으로서 Output Buffer를 순전히 SRAM으로 사용한 경우에 비하여 약 2배의 면적 감소를 가져온다. 이 제안된 구조는 8개의 10Gbps 입력 포트를 가지며 0.16um DRAM 기반 SoC(시스템-온-칩) 공정기술로 구현되었다. 칩 면적은 입력발생기를 포함하여 4mm x 9mm이다. 이 칩은 2002년 5월에 설계가 완성되었다.
