As the industry is growing up, it has led to the necessity of high volume data processing with high speed. With that flow, the exponential growth of the demands of internet, which requires the volume of the data transported on the backbone, has increases. To satisfy the requested capacity and speed, the transmission media has been converged to optical fibers.
Even though there have been many research efforts to solve the demands through system approaches such as wave-division multiplexing (WDM), the bottleneck is the electrical chips which form the system.
In the electrical chip domain, integration of high-speed analog functions and digital logic on a single chip or the system-on-chip (SoC) is becoming main-stream because it achieves low system power and small size. However, the SoC has intrinsic and fatal problem of substrate coupling noise between high fidelity analog circuits and noisy digital logic through the common silicon substrate.
To satisfy all conditions mentioned above, solution for digital noise, as well as high speed, is required.
In this thesis, design and implementation of gigabit CMOS transimpedance amplifier (TIA) for high-speed optical receiver application is described. In addition, to the intrinsic and fatal problem of system-on-chip (SoC) induced by substrate coupling noise between high fidelity analog circuits and noisy digital logic through the common silicon substrate, the approach to one-chip solution with digital noise free is proposed, implemented and verified with measurement.
A 1.25Gbps 80dBΩ fully differential transimpedance amplifier is implemented using 0.25㎛ CMOS and MCO (Multi-Chip-on-Oxide) process. MCO enables the integration of photodiode, TIA and planar inductors of Q=21.1 for shunt peaking on a oxidized silicon substrate. Its input noise current, inter-channel crosstalk and power dissipation are 0.13μA, ＜-40dB and 27mW, respectively. The chip size of MCO and TIA are 5×5㎟ and 0.13×0.17㎟, respectively.
고속 광 수신기 응용을 위한 Gigabit CMOS Transimpedance 증폭기(TIA) 가 0.25μ standard CMOS 공정을 이용하여 설계되고 구현되었다. 또한, System on chip (SoC) 에서의 치명적인 문제인 같은 실리콘 substrate안의 디지털 로직과 예민한 아날로그 회로사이의 커플링 잡음에 대하여, 디지탈으로 인한 노이즈의 영향을 받지 않는 단일 칩 구현 방법이 제안되고, 구현되었으며, 측정을 통해 검증되었다.
1.25Gbps의 동작 속도를 갖고, 80dBΩ의 차동 이득을 갖는 transimpedance 증폭기는 0.25μ CMOS와 MCO (Multi-Chip-on-Oxide) 공정을 이용하여 구현되었으며 MCO공정은 photodiode와 TIA 그리고 shunt peaking을 일으키기 위한 21.1의 Q값을 갖는 planar inductor를 하나의 Oxide silicon substrate 위에서의 집적을 가능하게 한다.
측정된 입력 잡음 전류 (input noise current) 는 0.13μA이며, 채널간의 cross talk은 -40dB보다 작고, 소모된 power는 27mW이다. MCO칩과 TIA 칩의 크기는 각각 5×5㎟, 0.13×0.17㎟이다.