In this thesis, interface trapped charges of PMOS, NMOS, and Pt/aluminum oxide/Si have been measured using quasi-static C-V method. Interface trapped charges are usually measured by capacitance-voltage(C-V), or conductance(G) method. Conductance method has been considered to be more sensitive than capacitance-voltage method, but when using this method, it isn't easy to evaluate the characteristics of interface between silicon and silicon oxide because it needs test-frequency variation in addition to the voltage variation. So, when monitoring the process variation, capacitance-voltage method is usually used.
However, traditional method, high frequency C-V method(also, known as Terman method), has its limitation, typically, on the accuracy of the measurement. High frequency C-V method use the stretch-out of the C-V curve to extract the information of the interface trapped charge, but it is very negligible when the MIS structure show the interface trapped charge of $~10^{10}eV^{-1}cm^{-2}$.
To overcome this limitation, quasi-static C-V method was proposed, and have several advantages over the high frequency C-V method, which include the contribution of interface trapped charge as a additional capacitance. After several examinations, quasi-static C-V method was found to have the accuracy of about $10^{10}eV^{-1}cm^{-2}$, which was slightly less than the conductance method(about $10^{9}eV^{-1}cm^{-2}$). With this range of accuracy, it is expected that the reliable extraction of the interface trapped charge is possible and this method can be used for the extraction of interface characteristics between silicon and insulator.
