서지주요정보
다단계 캐쉬 예측기를 이용한 프로세서의 캐쉬 에너지 소비 감소 = Reduction of cache energy consumption in processors using a multi-level cache predictor
서명 / 저자 다단계 캐쉬 예측기를 이용한 프로세서의 캐쉬 에너지 소비 감소 = Reduction of cache energy consumption in processors using a multi-level cache predictor / 최우성.
저자명 최우성 ; Choi, Woo-Seong
발행사항 [대전 : 한국과학기술원, 2001].
Online Access 원문보기 원문인쇄

소장정보

등록번호

8012013

소장위치/청구기호

학술문화관(문화관) 보존서고

MCS 01043

SMS전송

도서상태

이용가능

대출가능

반납예정일

등록번호

9007628

소장위치/청구기호

서울 학위논문 서가

MCS 01043 c. 2

SMS전송

도서상태

이용가능

대출가능

반납예정일

초록정보

Realistacally in a processor, on-chip cache is one of the most energy consuming part. About 15%~40% of the power is consumed by the on-chip cache. Many efforts are devoted to save the power consumed by the on-chip cache. Employing L0 cache is one example of such an effort. L0 cache is small cache that is placed between CPU and the L1 cache. To save the power consumed by the cache, frequently executed part of the program can be placed in the L0 cache so that more access can be made to the L0 cache. On an L0 cache hit, the system consumes less energy than conventional L1-L2 cache system because energy consumption of the L0 cache is much less than the L1 cache. And the L0 cache delay penalty is not matter since access latency of the L0 cache is same as or faster than the L1 cache. But on an L0 cache miss, the system must access L1 cache, therefore energy cannot be saved in this case. Moreover acces to the L1 cache is required after the access to L0 cache, which rises an additioinal L1 access delay. In this thesis, we propose Multi-Level Cache Predictor to use an L0 cache with less increase of delay penalty. Multi-Level Cache Predictor, employing Hit Pattern Clustering of the L0 cache, disables the L0 cache in the miss cluster and enables in the hit cluster. Simulation result showed that energy consumption and increase of delay have been reduced by this architeture.

서지기타정보

서지기타정보
청구기호 {MCS 01043
형태사항 [iv], 40 p. : 삽도 ; 26 cm
언어 한국어
일반주기 저자명의 영문표기 : Woo-Seong Choi
지도교수의 한글표기 : 조정완
지도교수의 영문표기 : Jung-Wan Cho
학위논문 학위논문(석사) - 한국과학기술원 : 전산학전공,
서지주기 참고문헌 : p. 39-40
주제 저전력
캐쉬
low power
cache
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