Modern microprocessor consumes a significant amount of energy and on-chip cache is a major source of energy dissipation in microprocessor. So it is important to reduce cache energy consumption for energy-efficient microprocessor.
In this paper, we propose an energy-efficient cache design that splits I-cache taking advantage of block`s bit-patterns. The proposed I-cache is composed of two parts of cache array; 0-major array and 1-major array. Blocks are allocated to either 0-major array or 1-major array according to their bit-majority. This scheme reduces the number of precharging, discharging and bit-switching transitions on the bitline.
We evaluate the access time and the energy consumption of our scheme using various cache configurations, and compare these with conventional designs. We also present the performance and energy tradeoffs that are involved in our new scheme.
