In computer graphics, a hardware designer has to understand the entire pipeline structure of a graphics hardware accelerator. Its pipeline structure becomes more complex. When designers developing the complex hardware, an environment in more abstract level may be helpful to them. HDL(Hardware Description Language)s give hardware designers the top down design methodology, but it is not enough to develop a large and complex system like a 3D graphics accelerator. In general, large systems like a graphics accelerator are initially described with an intuitive high-level behavioral language such as C. The design based on C may be re-coded into one of HDLs. If the goal of the design is developing the entire system, the work, re-coding the whole system into HDL description, is appropriate. However, if the goal of the design is developing a part of the system, designers will have some additional burden that they have to implement unnecessary parts.
This paper is about the research on co-simulation and co-verification environment suitable in developing computer graphics accelerator. This environment uses C++ and Verilog HDL. Finally, the focus of the environment is the interface between C++ and Verilog HDL. Making these interfaces is an additional burden. In order to discard this burden, a generator that makes interfaces is needed. The environment proposed in this paper may provide the high-level flexibility to the entire design flow. This environment based on VGS(Virtual Graphics System) of Multimedia VLSI laboratory in KAIST is composed of an interface generator and interface modules generated by it.