Reliability of high temperature processed polycrystalline silicon thin film transistors (poly-Si TFT’s) of high performance with electron cyclotron resonance (ECR) $N_2O$-plasma gate oxide under dc and ac stresses were investigated. As the stress power increases, the temperature in the channel would be raised up to very high point because of the poor conductivity of thick insulating quartz substrate. Therefore, for dc bias stress conditions, the degradation becomes serious as dissipating power increases. However, bias effect for the device degradation should be considered, as the stress bias increases and short channel effect (SCE) becomes serious. In this paper, the dependence of device degradation on gate bias, drain bias and channel length has been investigated.
Since poly-Si TFT’s are subjected to dynamic bias stress in actual system, it is very important to investigate the device degradation under dynamic stress conditions and to find the correlation between static stress and dynamic stress. Through stress test of various conditions, we have found that the degradation under dynamic stress is the same with the degradation under static stress for the same average power. This is valid for both gate and drain pulse stress conditions with the frequency above 10kHz. No enhanced degradation under dynamic stress has been observed in this study.
