In this thesis, a efficient architecture for digital IF and a digital filter supporting multi-standards are presented.
First, we proposed low-complexity digital IF-stage structure with the combination of 4-IF oversampling technique and interpolated finite impulse response(IFIR) filter design based on multirate algorithm. Proposed structure has very low-power dissipation owing to the reduction of hardware complexity and operating frequency.
A digital filter supporting multi-standards is designed in the form of cascade FIR/IIR by formulating Mixed Integer Linear Programming(MILP). In the FIR filter design, Cyclotomic Polynomial(CP) prefilter and 8 bit Interpolated Second Order Polynomial(ISOP) equalizer are used, and in the IIR case, additional 8 bit Interpolated First Order Polynomial(IFOP) and 4 bit Canonical Signed Digit(CSD) is used.
