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절연 기판 위에 형성한 다결정 실리콘 박막 트랜지스터의 수명 예측 = Lifetime estimation of polycrystalline silicon thin film transistors on insulating substrates
서명 / 저자 절연 기판 위에 형성한 다결정 실리콘 박막 트랜지스터의 수명 예측 = Lifetime estimation of polycrystalline silicon thin film transistors on insulating substrates / 양은진.
발행사항 [대전 : 한국과학기술원, 2000].
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8010482

소장위치/청구기호

학술문화관(문화관) 보존서고

MEE 00057

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Reliability and lifetime of high temperature processed polycrystalline silicon thin film transistors (Poly-Si TFT's) of high performance with electron cyclotron resonance (ECR) N2O-plasma gate oxide were investigated. Through stress test of various conditions, the degradations of poly-Si TFT's are found to be different with those of single crystalline silicon MOSFET's in which case, the degradation is mostly explained by hot-carrier effects. The degradation becomes serious as stress gate voltage and drain voltage become higher i.e., as dissipating power increases. As the power increases, the temperature in the channel would be raised, but it will be difficult for the heat in the channel to sink out because of the poor conductivity of thick insulating quartz substrate. Poly-Si TFT's have been applied to the circuit on LCD panel etc., so lifetime estimation is needed to know the reliability of device and circuit. Through the accelerated test of various power conditions, the lifetime of poly-Si TFT's on quartz could be estimated. As stress time goes, degradation progresses linearly with log-time scale. As stress power increases, device starts to degrade faster, and as stress power decreases, it has incubation time before degradation starts and after the incubation time, device is degraded linearly of log-time scale, too. The gradient of degradation along the time is found to be almost constant which is independent of stress power. Just the incubation time is directly dependent on stress power and determines device lifetime. So lifetime is directly related with the power. It is proportional to the P-m, where m is about 5. And Empirical model of lifetime is established with a function of any threshold voltage shift and dissipating power, which well matches with both directly measured and linearly extracted lifetime.

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서지기타정보
청구기호 {MEE 00057
형태사항 42 p. : 삽화 ; 26 cm
언어 한국어
일반주기 저자명의 영문표기 : Eun-Jin Yang
지도교수의 한글표기 : 한철희
공동교수의 한글표기 : 김충기
지도교수의 영문표기 : Chul-Hi Han
공동교수의 영문표기 : Choong-Ki Kim
학위논문 학위논문(석사) - 한국과학기술원 : 전기및전자공학전공,
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