A CMOS process which employs only single ion-implantation step for the p-well has been designed and tested This process is relatively easy to use and maintain in university laboratory environment since the expensive ion-implantation process can be carried out outside the university laboratory.
Process simulation and device simulation have been used to design the impurity diffusion and oxidation process. The targets for the threshold voltages are 1.2±0.6volt for NMOST and -1.2±0.6volt for PMOST.
During the test of the designed process, two major problems have been identified. The first problem is the masking oxide thickness for boron diffusion. It has been found that boron diffusion with BN975 planar diffusion source, at least 200nm oxide is needed to mask the boron diffusion. The second problem is boron penetration through gate oxide. The boron penetration problem has been solved by reducing the boron predeposition time, by reducing the thermal treatment after the boron predeposition, and also by using 20nm silicon nitride on top of 20nm thermal oxide for the gate insulator layer.
The modified process employing the remedies has been tested experimentally. Successful operation of NMOST and PMOST has been observed with the modified process providing the possibility of using this CMOS process for circuit fabrication and also as a test vehicle of the laboratory cleanliness.
