서지주요정보
ECR $N_2O$-플라즈마 게이트 산화막을 사용한 고성능 다결정 실리콘 박막 트랜지스터의 온도 영향과 안정성 향상에 관한 연구 = Temperature effects and stability improvements in high performance poly-Si TFT with ECR $N_2O$-plasma gate oxide
서명 / 저자 ECR $N_2O$-플라즈마 게이트 산화막을 사용한 고성능 다결정 실리콘 박막 트랜지스터의 온도 영향과 안정성 향상에 관한 연구 = Temperature effects and stability improvements in high performance poly-Si TFT with ECR $N_2O$-plasma gate oxide / 이충헌.
저자명 이충헌 ; Lee, Chung-Heon
발행사항 [대전 : 한국과학기술원, 1999].
Online Access 원문보기 원문인쇄

소장정보

등록번호

8009777

소장위치/청구기호

학술문화관(문화관) 보존서고

MEE 99093

SMS전송

도서상태

이용가능

대출가능

반납예정일

초록정보

Temperature effects and stability of high performance polysilicon thin-film transistors (poly-Si TFTs) with electron cyclotron resonance (ECR) $N_2O$-plasma gate oxide by both low- (LT) and high-temperature (HT) processes were investigated. The fabricated HT n-channel poly-Si TFT exhibits negative output conductance and decrease of drain current with increasing drain voltage at higher gate bias. This is found to be due to the high temperature rise during device operation caused by poor thermal conductivity of thick insulating substrate. The temperature in the channel region during operation is estimated by measuring the temperature dependence of resistance of the gate poly-Si. The temperature effects significantly enhance the degradation of threshold voltage under electrical stresses. The temperature rise is closely related with applied power, which is defined as a product of drain current and stress drain voltage. Although the mechanism of the threshold voltage shift is the breaking of the Si-H bond due to high temperature rise up to 480℃ , the fabricated n-channel poly-Si TFT exhibits very small degradation, which is attributed to the thermally stable Si-N and Si-O bonds. The fabricated TFT is expected to have lifetime of more than 10 years when the applied power is lower than 1.4 mWatt/㎛. On the other hand, instabilities of both HT and LT p-channel poly-Si TFT are found to be hot-carrier effects rather than temperature effects. Although stability of LT TFT is inferior to that of HT TFT, LT poly-Si TFT exhibits good device performance comparable to those of HT poly-Si TFT.

서지기타정보

서지기타정보
청구기호 {MEE 99093
형태사항 ii, 53 p. : 삽도 ; 26 cm
언어 한국어
일반주기 저자명의 영문표기 : Chung-Heon Lee
지도교수의 한글표기 : 한철회
지도교수의 영문표기 : Chul-Hi Han
학위논문 학위논문(석사) - 한국과학기술원 : 전기및전자공학과,
서지주기 참고문헌 : p. 52-53
주제 박막 트랜지스터
안정성
온도 영향
다결정 실리콘
ECR 플라즈마 산화막
TFT
Stability
Temperature effects
Polysilicon
ECR plasma oxide
QR CODE qr code