A planar polysilicon thin film transistor (TFT) EEPROM cell fabricated with a low temperature (＜400 ℃) process is demonstrated in this work. The gate electrodes of the TFT are connected to form the floating gate of the cell, while the source and drain of the larger TFT are connected to form the control gate. The cell is programmed and erased by Fowler-Nordheim tunneling. The threshold voltage of the cell can be shift by as much as 4 V after programming. This EEPROM cell has a excellent characteristics of endurance due to ECR $N_2O-plasma$ oxide for tunneling oxide and compatible process with poly-Si TFT process. This low temperature process technology is ideal for active matrix liquid crystal displays (AMLCD's) with large glass substrate, NVSRAM, 3-D VLSI, and large area electronics applications.