In order to support the Quality of Service(QoS) of each connection in ATM and to utilize network resources optimally, it is important to estimate the current status of networks. This thesis is concerned with the estimation of delay characteristics in ATM switches. A delay estimation mechanism is proposed in an ATM switch. In a single switch module the delay distribution of each connection is estimated by monitoring the buffer at the moment of each cell arrival and the upper bound of delay distribution of each connection is also estimated by monitoring the buffer at each cell time. For a multistage switch or a multiple node it is possible to obtain the end-to-end delay characteristics through convolutions if the correlation between the delays of successive node is negligible. A fast convolution mechanism is also proposed in order to reduce the number of multiplications and the amount of information to transmit. The feasibility of the mechanism is verified by simulation for various types of CBR and VBR traffic load.
