Silicon substrate is widely used in packaging areas because of its advantages of lower cost and good thermal conductivity to help remove heat and to maintain low IC junction temperatures. The semi-conducting nature of silicon substrate, however, has prohibited the fabrication of high performance passive elements in silicon substrate.
A selectively oxidized porous silicon (SOPS) substrate was proposed to use the microwave power multi-chip packaging area. In this work, anodization of p-type silicon was carried out under the condition of 2, 6, 10, 30 and 50mA/㎠ in electrolyte solution of HF(48 w/o):$C_2H_5OH$=1:1.
Firstly, PIPS (pulse injected porous silicon) layer was obtained by novel pulse modulation method. This new method has an advantage of higher growth rate of porous silicon. SEPS (selective porous silicon) layer is successfully implemented by patterning of Cr/photoresist and n-type silicon mask of phosphorus diffusion. And, the thick oxide film had to be obtained by a short-time-oxidation process of porous silicon, because the phenomenon of oxidation for porous silicon is the reaction of sidewall of trenches.
The porosity of porous silicon is most important factor but the porosity measurement of silicon weight loss (the gravimetric method) is contained the high error rate. In the porosity calculation of porous silicon, new exact method(JRM method) of hole counting is proposed from the tetravalent dissolution reaction of porous silicon and the proposed reaction factor $M_{si}$.
Using the OPS (oxidized porous silicon) substrate with thick silicon dioxide layer, high performance passive devices such as spiral planar inductors, coplanar waveguide (CPW) were fabricated and characterized. For GaAs MMIC chip interconnection, Au-wire bonding with 25μm-diameter is characterized.
Thick oxide layer increases resonant frequency and maximum Q factor in planar inductor because of the low parasitic capacitance between inductor metal and the substrate. For 6.29nH inductor(the metal width and spacing is 5μm), resonant frequency of 13.8GHz, maximum Q factors of 13.3 and 0.65dB insertion loss at 4GHz are obtained, which are very comparable to those available in GaAs MMIC.
CPW and Au-bonding wire was characterized on OPS substrate with 20μm-$SiO_2$ layer. The insertion loss of CPW of 2mm length is less than 0.21dB at 4GHz. The return loss of CPW of 2mm length is less than -22dB. The insertion loss of wire binding of 1000μm loop length is less than 0.19dB. The return loss of wire bonding of 1000μm loop length is less than -26dB. From the this result, Au-bonding wire on OPS substrate can be used for chip interconnection at least up to 10GHz.
The flip-chip equipment is realized by Infrared rays (IR) align method. Flip-chip equipment is consisted of three basic parts: main flip-chip bonder (heating source, Quartz plates, xyzΘ motion driver), control part(temperature controller, motion controller) and infrared rays detection part (IR microscope, IR detection camera, image processing computer). The flip-chip equipment of IR align method have the advantage of application to front-back aligner which is required in process of backside via hole etching of GaAs devices.
Flip-chip experiment of GaAs test chip and OPS substrate had try by flip-chip equipment. Thermal evaporated Indium solder bump is fabricated successfully. In flip-chip experiment, the reflow process of 180 C has enhanced from the result of resistance of indium bump.
SOPS substrate is consist of silicon part for chip packing and OPS part for integration of passive elements like inductors, MIM capacitors, resistors and CPW. Active devices on implanted on GaAs or silicon substrates are attached by flip-chip or wire-bonding technique. This structure provides many advantages at microwave frequency such as neglecting of semiconducting nature of silicon and low signal attenuation by thick $SiO_2$ of OPS layer, advanced process of silicon, low cost of silicon substrate, flip-chip technique, uniplanar structure and so on.
From this point, SOPS substrate was used in microwave multichip packaging for two GaAs broadband amplifier interconnection and transmitter at L-band, successfully.
본 논문에서는 실리콘 기판을 이용하여 선택적 양극화 반응 및 산화과정을 통해 선택적 산화된 다공성 실리콘층을 형성하였다. 저가격, 높은 공정기술, 높은 열전도도등의 장점을 지니고 있는 실리콘 기판을 두꺼운 산화된 다공성 실리콘 층을 형성함으로써 초고주파 대역에서의 실리콘 기판의 반전도특성을 효과적으로 제거될 수 있음을 초고성능 평면 인덕터 및 낮은 손실을 지니는 Coplanar waveguide를 제작함으로써 그 효과를 증명하였다.
실리콘 기판의 양극화 반응에 있어서 기존의 직류주입 양극화 반응에 대해 펄스주입 양극화 반응을 처음으로 제안하고 실험을 시도하였으며, 그 결과 양극화 반응력의 증가에 의한 다공성 실리콘의 성장률이 증가함을 보였다. 또한, 다공성 실리콘의 가장 중요한 인수인 다공도 계산을 기존의 무게차이의 측정 방법인 gravimetric 방법에 대해 Tetravalent dissolution 반응 및 실리콘 단위 셀에서의 반응인수 Msi를 도입함으로써 JRM(J:전류밀도, R:다공성 실리콘 성장율, M:반응인수) 방법을 처음으로 유도하여 제시하였으며, 각 양극화 실험조건에 따른 다공성 실리콘 기판의 다공도를 계산하였다. 이 실험식은 실리콘 기판의 불순물 농도 및 불산용액의 비율, 전류 밀도에 따른 복잡한 양극화 반응조건에 따른 실리콘의 다공도 계산 및 원하는 다공도를 실현할 수 있을 것으로 기대된다.
산화된 다공성 실리콘 기판으로 자체 제작된 후면 정렬 포토리소그래피가 가능한 자외선 정열 방식의 플립칩 장비를 제작하고 인듐범퍼를 이용한 플립칩 실험을 행하였다.
선택적 산화된 다공성 실리콘 기판을 이용하여 실리콘 부분의 높은 열전도도 특성 및 산화된 다공성 실리콘 층의 낮은 유전손실을 복합적으로 이용한 초고주파대역에서의 멀티칩 패키지에 응용하기 위해 시도되었다. MMIC 기술로 제작된 광대역 갈륨비소 증폭기칩과 저항, 커패시터, 인덕터를 집적한 선택적 산화된 다공성 실리콘 기판을 이용하여 직결연결한 다중칩 증폭기를 실현하고, 갈륨비소 전압제어공진기와 주파수혼합기 및 증폭기를 산화된 다공성 실리콘 기판에 다중칩 패키징하여 초고주파 송신단을 성공적으로 실현하였다.
