고속 SDRAM을 위한 스큐 제거 delay locked loop = A deskewing delay locked loop for high speed SDRAM

• 서명 / 저자: 고속 SDRAM을 위한 스큐 제거 delay locked loop = A deskewing delay locked loop for high speed SDRAM / 남형식.
• 발행사항: [대전 : 한국과학기술원, 1998].

This paper describes a delay-locked loop that can be used as a deskewing element in SDRAM. Using the variable locking edge scheme to eliminate the limit which is generated by the minimum value of voltage controlled delay line, this DLL increases locking speed and I/O bandwidth. This DLL circuit is simulated with the model parameter of 0.45㎛ CMOS process. The range of input frequency is from 20 MHz to 250 MHz and the clock skew is less than 200 ps. The locking time is less than 400 ns. SDRAM with this scheme can be used in various applications because of wide bandwidth.

• 형태사항: ii, [70] p. : 삽화 ; 26 cm
• 언어: 한국어
• 일반주기: 저자명의 영문표기 : Hyoung-Sik Nam ; 지도교수의 한글표기 : 김범섭 ; 지도교수의 영문표기 : Beom-Sup Kim
• 학위논문: 학위논문(석사) - 한국과학기술원 : 전기및전자공학과,
• 서지주기: 참고문헌 수록