In this thesis work, we implement the 2400bps all-digital modem using a digital signal processor (DSP) chip. The modem algorithm is designed based on the ITU-T V.26ter specification and modified to transmit telephone channel voice signal. The usual algorithms of the V.26ter modem consist of symbol timing recovery, adaptive equalization, carrier recovery, and echo cancellation, etc.
Trellis-coded modulation (TCM) and cyclic equalization are added to the V.26ter modem. The Viterbi algorithm, a soft-decision maximum-likelihood sequence decoding algorithm, is used as a method of decoding TCM. The 8-PSK with the 8-state TCM acheives a coding gain of 3-4dB, compared with the uncoded QPSK. This coding gain is obtained without bandwidth expansion or reduction of the data rate. Cyclic equalization for very fast start-up of the adaptive equalizer is adopted. The sequence having constant amplitude and zero autocorrelation (CAZAC), whose period in symbols is equal to the number of the equalizer taps, is used for training. Cyclic equalization using the CAZAC sequence converges more rapidly for about 200-300 symbols than the LMS algorithm.
The modem algorithm is optimized for real-time implementation. For the implementation of the modem, we use a TMS320C50 DSP chip.
