Design and implementation of finite impulse response (FIR) filters and filter banks have received considerable attention in digital signal processing. In this disertation, we consider efficient design and implementation of FIR filters and filter banks: specifically sparse FIR filters and FIR filters with powers-of-two coefficients, often referred to as 2PFIR filters, are considered for computationally efficient design and implementation, respectively, and new VLSI structures for discrete wavelet transform (DWT) are developed as a special case of filter bank implementation.
First an optimization problem for designing a linear phase sparse FIR filters with minimal complexity is formulated. Specifically a cost function is defined on the number of nonzero coefficients and their positions so that the optimal solution of the problem should guarantee minimal number of nonzero coefficients and minimal required delays. The formulated problem is then solved by mixed integer linear programming (MILP). Design examples illustrate that the proposed method is useful for designing a wide range of filter types, and can outperform subset selection-based design methods.
We also develop an alternative approach to the efficient implementation of 2PFIR filters requiring less hardwares than the conventional ones. The proposed approach extracts common sub-expressions (CSEs) from filter coefficients by first decomposing the set of all CSD coefficients into some subsets having CSEs, and then comparing each subsets with filter coefficients. In this approach, we examine all possible signed digit codes with minimal number of nonzero digits, called minimal signed digit (MSD) codes, when extracting CSEs. Since the set of all MSD codes encompasses the CSD codes as a special case, the proposed approach can be more effective in reducing the number of additions than the previous one. Design example illustrates the sharing adders for extracted CSEs can reduce the number of adders required for implementing coefficients by more than 30 %, and extention of the search range from the CSD codes to the MSD codes provides additional reduction of adders.
Finally, we develop a scalable VLSI architecture employing a two channel quadrature mirror filter (QMF) lattice for the one-dimensional (1-D) discrete wavelet transform (DWT). We begin with the development of systematic scheduling, which determines the filtering instants of each resolution level, on the basis of a binary tree. Then input-output relation between lattices of the QMF bank is derived; and a new structure for the data format converter (DFC) which controls the data-transfer between resolution levels is proposed. In addition, implementation of a delay control unit (DCU) that controls the delay between lattices of the QMF is proposed. The structures for DFC and DCU are regular, scalable and require minimum number of registers, and thereby lead to an efficient and scalable architecture for the DWT. A scalable architecture for the inverse DWT is also developed in a similar manner, and at last pipelining of the proposed architecture is considered. The approach introduced here can be directly applicable to M-ary tree structured filter bank.
