In this paper, tantalum oxide films for DRAM capacitor have been deposited by Cycle-CVD. Cycle-CVD consists of sequential injections of $Ta(OC_2H_5)_5$ pulse, Ar pulse, $NH_3$ pulse and Ar pulse. By separation between $Ta(OC_2H_5)_5$ and $NH_3$ using Ar, the homogeneous reactions between $Ta(OC_2H_5)_5$ and $NH_3$ are prevented. Tantalum oxide films was deposited at temperature range higher than $Ta(OC_2H_5)_5$ and $NH_3$ CVD regime and lower than decomposition regime. In this range, the film growth mechanism was Atomic Layer Deposition (ALD). When the $Ta(OC_2H_5)_5$ injection time was varied from 1 to 60 seconds, the thickness per cycle was saturated above 20 seconds. Changes of purge time between $Ta(OC_2H_5)_5$ and $NH_3$ were not affected the thickness/cycle of films. The thickness per cycle was 1.7 Å/cycle with varied cycle numbers so we can controll the film thickness in detail.
The leakage current mechanism of as-depositied films was Space-Charge-Limited conduction. The current density of as-deposited film was proportional to a square of the electric field.
After annealing, the conduction mechanism was changed from Space-Charge-Limited conduction to hopping conduction. Annealing treatements were carried out at 600, 700, 800, 900℃ for 10min in $O_2$ at 300 torr. In hopping conduction, current density is propotional to electric field. During annealing treatment, impurity contents as C, N, H and defect density were decreased. And the density of film and O/Ta ratio were increased. These are the reason of the change of leakage conduction mechanism and decrease of leakage current after annealing.
Leakage current of annealed film depended on the annealing temperaure. As higher annealing temperaure, impurities decrease more and more, so leakage current decreases. But when the temperature is too high so tantalum oxide films are fully crystallized, grain boundaries become the path of leakage current. Then leakgae current after annealing would be increase with increase of annealing temperature. So There was one annealing temperature to have optimum leakage chracteristics. In the case of 150 Å tantalum oxide films, it was 800℃.
Dielectric constant $ε_r$ was 11.8 for as-deposited tantalum oxide film and 13.3 for annealed at 800℃. The dielectric constant was increased after annealing and it may be caused by the decrease of impurity before crystallization.
1. $Ta(OC_2H_5)_5$와 $NH_3$를 이용하여 Cycle-CVD법으로 tantalum oxide를 증착하였다.
1) 250, 265℃에서 $Ta(OC_2H_5)_5$ : Ar : $NH_3$ : Ar의 sequence에서 $Ta(OC_2H_5)_5$ 공급시간을 변화시켰을 때, 20초 이상에서 cycle 당 두께가 saturation 되었다.
2) Ar purge 시간을 변화시켰을 때 박막의 cycle 당 두께는 변함이 없었다.
3) 기판 온도 250 ~ 265℃에서, 박막의 증착 기구는 Atomic Layer Deposition(ALD)였다.
4)265℃에서 $Ta(OC_2H_5)_5$ : Ar : $NH_3$ : Ar = 20sec : 5sec : 5sec : 5sec의 sequence로 증착시 cycle 당 두께는 1.7 Å이었다.
2. Annealing 전 후의 박막의 특성 변화는 다음과 같았다.
1) Annealing 전의 누설 전류 기구는 Space-Charge-Limited conduction으로서 current density J는 electric field E의 제곱에 비례하였다. Annealing 후 누설 전류 기구는 hopping conduction으로 current density J는 electric field E에 비례하였다.
2) Annealing 후 누설 전류 기구는 hopping conduction으로 current density J는 electric field E에 비례하였다. Annealing 처리후 누설전류기구가 Space - Charge - Limited conduction에서 hopping conduction으로 바뀐 것은 annealing 처리시 불순물 감소, O vacancy 보수등의 박막 내부의 charge 감소이다.
3) Annealing 처리는 annealing으로 인한 불순물 감소로 인한 누설 전류 감소와 결정화로 인한 결정입계 누설 전류 증가의 상충되는 효과를 가지며, 박막의 두께에 따라서 최적의 효과를 얻을 수 있는 annealing온도가 결정된다. As-dep 박막의 C 5at%, N 12at%의 함유량에서 900℃ annealing 후 C 4at%, N 3at%로 감소하였다. 두께 150 Å의 tantalum oxide 박막의 경우, annealing 온도가 800℃였을 때 누설 전류 특성이 가장 좋았다.
4) 265℃에서 cycle-CVD법으로 증착된 박막의 유전 상수값 $ε_r$은 annealing 전 11.8, annealing 후 13.3로, annealing 후 증가하였다.