This paper describes the efficient design verification method using H/W emulation.
In general, Design verification is performed using software simulation. But, the more design complexity increase, the more simulation speed is decreased. Furthermore, the increasement of I/O terminal make it difficult the protocol verification on target system.
And, the increasement in design complexity needs more test vector to verify. So, the verification time is above design time.
This paper describes the advantage and disadvantage, problems and solutions in H/W emulation. In the following chapters, I describe design used in emulation in brief, problems and solutions in each emulation process and method that find bugs in design. By H/W emulation on our design, we can find bugs that have long life time and boot operating system (DOS 6.0) and other DOS applications.
