In this thesis, H/W and S/W implementations of decoders using block codes for random error correction are described and the performance of the codes is obtained. These can mainly be used in space communication or mobile telephones. We implement a decoder for the(63,48) cyclic code using the FPGA, XC3064. Moreover we introduce the block of a digital PLL which reduces the phase margin, and is really useful for designing a decoding circuit.
By implementing using S/W algorithm, complex logic circuits are eliminated and then we can easily construct a compact-sized products. The data rate of 2400 bps and the carrier frequency of 800MHz are used for evaluation of the performance. The Bit Error Rate(BER) performance of the decoding algorithm is about 2dB superior to that of the uncoded case.
