서지주요정보
VLIW 프로세서의 효율적인 Prefetch 구조의 설계 = The design of effective prefetch structure for VLIW processor
서명 / 저자 VLIW 프로세서의 효율적인 Prefetch 구조의 설계 = The design of effective prefetch structure for VLIW processor / 한경남.
저자명 한경남 ; Han, Kyung-Nam
발행사항 [대전 : 한국과학기술원, 1997].
Online Access 원문보기 원문인쇄

소장정보

등록번호

8007815

소장위치/청구기호

학술문화관(문화관) 보존서고

MEE 97104

SMS전송

도서상태

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반납예정일

초록정보

This thesis covers an instruction prefetch structure, particularly suited for a VLIW processor, and proposes new DRAM architecture to achieve better performance and greater efficiency. The VLIW processor uses instruction level parallelism(ILP), so it can execute several instructions in one clock cycle. Sometimes this can cause problems in transferring data via external buses because the width of external buses is less than that of long instruction word. If a cache miss occurs, processor must contact with external memory that usually consists of DRAM, and therefore the miss penalty time is significantly larger in the processors that uses ILP technology. Although there are many methods to solve this problem from the viewpoint of architectural design, the use of the proposed DRAM architecture is suggested. Compare logic and block buffers are added up with standard DRAM so that the memory has simple instruction prediction functionality, that transfers sequential instruction lines restlessly until one of the branch instructions are met. The prefetch structure that used this DRAM architecture was simulated, and the results are presented and analyzed.

서지기타정보

서지기타정보
청구기호 {MEE 97104
형태사항 iii, 76 p. : 삽도 ; 26 cm
언어 한국어
일반주기 저자명의 영문표기 : Kyung-Nam Han
지도교수의 한글표기 : 김이섭
지도교수의 영문표기 : Lee-Sup Kim
학위논문 학위논문(석사) - 한국과학기술원 : 전기및전자공학과,
서지주기 참고문헌 : p. 75-76
주제 D램
메모리
프리페치
VLIW
캐쉬
DRAM
Memory
Prefetch
VLIW
Cache
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