This thesis covers an instruction prefetch structure, particularly suited for a VLIW processor, and proposes new DRAM architecture to achieve better performance and greater efficiency.
The VLIW processor uses instruction level parallelism(ILP), so it can execute several instructions in one clock cycle. Sometimes this can cause problems in transferring data via external buses because the width of external buses is less than that of long instruction word. If a cache miss occurs, processor must contact with external memory that usually consists of DRAM, and therefore the miss penalty time is significantly larger in the processors that uses ILP technology. Although there are many methods to solve this problem from the viewpoint of architectural design, the use of the proposed DRAM architecture is suggested.
Compare logic and block buffers are added up with standard DRAM so that the memory has simple instruction prediction functionality, that transfers sequential instruction lines restlessly until one of the branch instructions are met. The prefetch structure that used this DRAM architecture was simulated, and the results are presented and analyzed.
