In recent days, there is strong demand for low power design especially for portable multimedia systems. In this thesis, 32bits multiplier has been designed with low power design concept. Appropriate methods to reduce the power consumption have been adopted in each design levels- algorithm, architecture, logic, circuit, and layout. Particularly, a new four-two compressor circuit which is majority of multiplier circuit has been proposed. The proposed four-two compressor circuit consists of pass transistors so that area, that is physical capacitance, could be greatly reduced. With this proposed circuit, 17% power reduction has been achieved. In addition to this low power characteristic, the multiplier has a shared architecture for fixed and floating point multiplication with hardware overload less than 1%.
