VLIW(Very Long Instruction Word) processors issue multiple instructions in one clock cycle. Multiple-issue improves the performance of processors further than conventional single-issue processors. To exploit the benefit of multiple-issue, there should be enough parallelism among the instructions that are executed in VLIW processors. It is pipelining that makes it more difficult to find the instruction-level parallelism on application programs. Pipelining causes hazards that hinder parallel execution of programs. Among three kinds of data hazards, RAW(Read After Write) hazards occur most frequently in VLIW processors.
Forwarding is a widely used technique to reduce the performance degradation caused by RAW hazards. However, forwarding requires too much area of the chip when it is applied to VLIW processors because the area of forwarding circuits is proportional to square of the number of functional units and VLIW processors have multiple functional units in order to issue multiple instructions per clock cycle. In this thesis, static forwarding is proposed to reduce the overhead cost of forwarding circuits. Static forwarding does not restrict the forwarding paths of processors. It uses the register file that is modified for forwarding operation. And it needs compiler to detect RAW hazards and modify register operands. VLIW Processor Model is designed to verify static forwarding. This thesis describes the operation of static forwarding and the comparison with the conventional forwarding.
