In a high-performance 3D graphics system, the bus bottleneck between a rendering engine and a frame memory is a serious problem due to high bandwidth requirement between them, and it consequently limits overall system performance. As a method of overcoming this problem, some functions of the rendering engine can be merged into the frame memory to take advantage of accessing the wide internal memory bus.
In this thesis, we propose a new structure of the frame memory for the 3D graphics system which can perform parallel horizontal interpolation, parallel Z-comparison, and parallel pixel writing in a single frame memory chip. It raises the pixel writing rate about four times higher than the conventional frame memory architecture. The newly proposed structure of the frame memory has been designed with 0.6㎛-one poly, two metal technology. The chip size is 16.2mm × 8.8mm. We have used COMPASS design automation tools for layout generation and HSPICE simulator for circuit simulation. The performance of the 3D graphics system adopting this frame memory has been measured by the architecture simulator written by C language. This layout will be entered into fabrication process soon.
