Most recent computer architectures are moving to 64-bit virtual address spaces, and this movement actuates the discussion of single address space operating system. Under these new environments, the multilevel pagetable which is the most popular pagetable mechanism of conventional systems needs performance revaluation. But, former evaluations of the multilevel pagetable assumed too simple simulation model and had little consideration for micro-processor's MMU.
In this thesis, we evaluate the multilevel pagetable using a precise simulation model. This model includes recursive characteristics of address translation, and consideration of TLB and cache effects. The result of our trace driven simulation shows that page faults of pagetable itself is the most important source of performance degradation, and the cache miss of pagetable and tree traverse cost are another source. And the sparsity of single address space operating system increases the size of multilevel pagetable. To improve the performance of multilevel pagetable, each node of pagetable tree must be about the same size of the base page.
