We have fabricated the polycrystalline silicon thin film transistors (poly-Si TFT's) by solid state crystallization(SPC) of amorphous films deposited by low pressure chemical vapor deposition(LPCVD). The effects of hydrogenation on the output characteristics and leakage current of the poly-Si TFT's have been studied. By using two different precursor films, one is from silane and the other is from disilane, we got the dependency on the grain size of the poly-Si films. Because hydrogenation cannot passivate all the defects in the grain boundary, it is important to get the films of large grain size. We have bias-stressed hydrogen passivated polycrystalline silicon thin-film transistors varying the bias condition and measured the change in the field-effect conductance activation energy as a result of the bias stress. For stress by a high gate bias voltage, a slight broadening occurs in the activation energy curve, while stress by a low gate bias voltage gives rise to a shoulder at low gate voltage, which could be explained by the defect states localized at the region near drain. Numerical calculation has conformed that the change in activation energy is due to defect generation in poly-Si and if stressed by low gate voltage, defects are localized at near the drain region. The energy distribution of the defects cannot be obtained accurately, but its energy position is higher than 0.2 eV above mid-gap.