서지주요정보
1GHz low noise frequency synthesizer design for digital mobile communication using monolithic CMOS technology = 디지탈 이동통신에 적합한 monolithic CMOS 기술을 이용한 1GHz 급 저잡음 주파수 합성기의 설계
서명 / 저자 1GHz low noise frequency synthesizer design for digital mobile communication using monolithic CMOS technology = 디지탈 이동통신에 적합한 monolithic CMOS 기술을 이용한 1GHz 급 저잡음 주파수 합성기의 설계 / Seog-Jun Lee.
저자명 Lee, Seog-Jun ; 이석준
발행사항 [대전 : 한국과학기술원, 1996].
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소장정보

등록번호

8006923

소장위치/청구기호

학술문화관(문화관) 보존서고

DEE 96038

SMS전송

도서상태

이용가능

대출가능

반납예정일

초록정보

The implementation of a single-chip, low noise CMOS PLL frequency synthesizer for wireless communication applications has been presented. The circuit is composed of three main components, i.e., a Voltage-Controlled Oscillator (VCO), 1 / 7, 8 dual-modulus prescaler and a Phase-Frequency Detector (PFD). The circuit is fully integrated with the exception of the loop filter components in a standard digital 0.8㎛ CMOS process. To be immune to noise, all the circuits in the synthesizer use the differential schemes and the digital parts are designed by the static one. A new high speed low noise VCO with precise signal swing control has been proposed. While the VCO output frequency can be controlled by the current of the each delay cell, each of the maximum and the minimum voltage levels can be controlled precisely by the respective reference voltage. Since this overhead circuit does not increase the output load, we succeed to obtain VCO operating in GHz range. With this method, the output swing levels are controllable independently of the power supply and the ground and thus a level shifter and an amplifier are not needed. Another new high frequency ring oscillator suitable for multi-phase clock generation has been proposed. The ring oscillator consists of inverters with negative delay elements that are derived from the other nodes in the ring oscillator circuit. In this way, it is possible to obtain the cell delay of the ring oscillator which is smaller than the fundamental inverter delay. Simulations show that the resulting operating frequencies can be twice as high as those obtainable in the conventional approaches. A new VCO combined with the new ring oscillator has been also studied. Simulation shows that the 25% higher operating frequency can be obtained compared with the conventional approach. A new D flip-flop with a single clock, differential static scheme for a dual-modulus prescaler has also been proposed. The maximum operating frequency of 1.45GHz was achieved and the output jitter of the proposed scheme was 35% less than that of the true-single phase clocking approach. A new D flip-flop in dead-zone free PFD was also proposed. CMOS monolithic PLL frequency synthesizer incorporating above new features has been fabricated using 0.8㎛ single poly and double metal process. The fabricated VCO shows a center frequency of 800MHz and the tuning range of 25%. The supply sensitivity of the VCO free-running frequency is 2.3%/V, and the temperature coefficient of that is 1200ppm/℃. The measured frequency synthesizer performance has a locking range of 700MHz to 1GHz with -80dBc/Hz phase noise at a 100KHz carrier offset. The test chip has an active area of 0.34㎟ and consumes 125mW at maximum frequency from a 5V supply. Our result shows the feasibility of a monolithic CMOS PLL frequency synthesizer suitable for mobile communication in scaled down CMOS technologies.

서지기타정보

서지기타정보
청구기호 {DEE 96038
형태사항 vi, 112 p. : 삽도 ; 26 cm
언어 영어
일반주기 저자명의 한글표기 : 이석준
지도교수의 영문표기 : Kwy-Ro Lee
지도교수의 한글표기 : 이귀로
학위논문 학위논문(박사) - 한국과학기술원 : 전기및전자공학과,
서지주기 Reference : p. 107-114
주제 Frequency synthesizer
Mobile communication
Voltage controlled oscillator
주파수 합성기
이동 통신
전압제어발진기
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