The top-down design methodology using a hardware description language like VHDL has gained popularity because of its higher productivity than the previous one. However, as the size of a target system becomes larger and its complexity increases continuously, it is widely recognized that a new design methodology is required.
In this thesis, we propose a hardware modeling formalism called HDEVS which is based on DEVS formalism. The DEVS formalism is a set-theoretic formalism which describes discrete event systems in a hierarchical and modular manner. Explicit use of the formalism precludes any ambiguity and enables the formal verification of a target system. In addition, using the HDEVS formalism provides fast simulation speed, independent module testing, intelligent and systematic model management using a model base and a system entity base, integrated modeling of inhomogeneous environments and graphical modeling. Thus we can develop a complex system rapidly with less errors in the integration. Also, the translation method of HDEVS model to synthesizable VHDL code is proposed and implemented. This translated VHDL code can be used in the stable synthesis environment which is standardized in the industry.